The present invention pertains generally to computing systems. Specifically, the present invention relates to memory management systems and more particularly to a method and an apparatus for reducing latencies associated with accessing a page of memory by a processor using a translation look aside buffer in computer memory systems that utilize virtual memory addressing.
A virtual memory system is one which allows addressing of very large amounts of memory, even though the main memory of the system encompasses a smaller address space. Virtual memory systems provide this capability by defining memory management units, in particular, pages or segments, have virtual memory address and corresponding physical memory addresses. A particular virtual memory address may be in main memory or in slower alternate memory, such as disk space. If a virtual address maps to a physical address of data is main memory, the information is readily accessed and utilized. If the physical address indicates that the page corresponding to the virtual address is located in the alternate memory, the page is transferred or swapped into main memory where the data can be accessed. The transfer typically necessitates that other information be swapped out of main memory back to the alternate memory to make room for the new information. This transfer is typically performed under the control of the memory management unit as either hardware or software.
To increase the speed of virtual memory accesses, cache memories are also included to store recently used data and instructions. These caches are first accessed before accessing main memory for the information requested. These caches may be virtually addressed or physically addressed. However, cache memories accessed in accordance with the physical address necessitates the process of virtual to physical access translation prior to checking the cache as well as the main memory.
The paging process, that is, the process of swapping pages, relies on a data structure that is indexed by the pages of memory. This data structure contains a physical address of the memory to be accessed according to the virtual address provided. This data structure containing the physical page addresses usually takes the form of a page table indexed by virtual page numbers, the size of the tables, the number of pages and the virtual memory space. Page tables are usually so large that they are stored in the main memory and are often paged themselves. This means that every memory access takes at least one or more times as long as one memory access is needed to obtain the physical address and a second access is needed to obtain the data.
One technique used in minimizing the cost of access time is to save the last translation performed so that the mapping process is skipped if the current address refers to the same page as the last one. In addition, to save additional time, advantage is taken of the principal of locality that is utilized for caches. If the references have locality, the address translations for references must also have locality. By keeping these address translations in a special cache, a memory access rarely requires a second access to translate the address. This special address translation cache is referred to as a translation look aside buffer, or xe2x80x9cTLBxe2x80x9d. A TLB entry is like a cache entry wherein a tag portion hold portions of the virtual address and the data portion holds a physical page frame number, protection fields, use bits, and a modified or dirty bit. An example of a typical TLB data structure 100 is illustrated in FIG. 1.
A number of different methods and techniques are available for increasing the speed of accesses to virtual memory. In one method, a more heavily pipelined memory access is utilized, wherein the TLB access is performed one step ahead of the pipeline. Another approach is to match virtual addresses directly. Such caches are referred to as virtual caches. This eliminates the TLB translation time from a cache hit access situation. However, unfortunately, one drawback is that the process is very time consuming and needs to be performed for each virtual address regardless of address locality.
It should be noted that additional discussions regarding TLBs can be found in David A. Patterson and John L. Hennessey, Computer Architecture, A Qualitative Approach Second Edition, (Morgan Kaufmann Publishing), pages 439-457.
In view of the foregoing, it should be apparent that methods and apparatus for reducing memory access latency in a virtual memory environment is desirable.
According to the present invention, a method for reducing memory access latency in a virtual memory based system is disclosed.
In one aspect of the invention, an apparatus for reducing memory access latency in a virtual memory based system is disclosed. The apparatus includes a processor arranged to perform executable instructions, a main memory suitably coupled to the processor arranged to store executable instructions that are performed by the processor, a cache memory coupled to the processor and the main memory arranged to store a subset of recently used instructions, wherein the cache memory is located temporally closer to the processor than the main memory. The apparatus also includes a TLB page cache suitably arranged to store a TLB page, wherein under the direction of the processor, a new TLB page corresponding to a new TLB entry is moved temporally closer to the processor by moving from the main memory to the TLB page cache, wherein the TLB page cache is proximally closer to the processor than the main memory, and wherein a TLB page cache entry in the TLB page cache points to an associated TLB page.